Field of the Invention
The invention relates to a semiconductor module, e.g. a semiconductor module having a plurality of signal paths for carrying external signals which each contain a setup and hold circuit on the basis of a latch circuit with a full latch and a logic circuit.
Accordingly, the present invention lies in the field of setting the setup and hold circuit on the signal paths of a (symmetrical) semiconductor module. The setup and hold times should be set or centered in such a way that the semiconductor module ensures fast internal signal processing. For this purpose, two procedures or configurations of the setup and hold circuit of the semiconductor module have been known hitherto.
The first procedure provides the configuration of a full latch (circuit for complete latching of signals) near to the start of the signal path, i.e. near to an input to the latter. The configuration of the full latch allows the setup and hold times to be centered without difficulty since, at this point on the signal path, there are typically only a small number of signals present which, moreover, cover very similar path lengths up to the full latch. However, the external setup time of the signal (called an external signal in the present case) cannot be utilized for internal fast signal processing because the signals must wait for the clock of the full latch before the latch operation in the full latch.
A second procedure provides for a full latch in the setup and hold circuit of the semiconductor module at a point on the signal path which is located further downstream. In other words, the signals carried on the signal path are not latched until they have already passed through a considerable stretch of the signal path, which is typically characterized by a plurality of logic circuits (when mention is made of logic circuits in the singular in the present case, this is also intended to encompass a plurality of logic circuits). Since the clock signal path (clock path) to the full latch is shorter than the relatively long stretch of the signal path on which the external signal is carried, the clock signal can temporally catch up with the external signal on its stretch to the full latch, so that at the full latch (complete latching) the signals do not have to wait for the clock signal for a long time. This enables the external setup time of the signal to be utilized in favor of internal fast signal processing. However, since, in the course of the long stretch of the signal path up to the full latch, i.e. during the processing of the external signal by logic circuits, the originally few signals have been split into many sub-signals which, moreover, also pass through very different path lengths up to the full latch, the centering of the setup and hold times in this way is complicated and problematic.
The two previous procedures for centering the setup and hold times or the two previous latch contents are thus able to utilize only either the realization of problem-free setting of the setup and hold times or the utilization of the external setup time for fast internal signal processing.
U.S. Pat. No. 5,949,258 discloses a semiconductor module having two latch circuits that are disposed on a signal path and each perform a complete latch operation with the setting of the setup and hold times.
It is accordingly an object of the invention to provide a semiconductor module which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which ensures fast internal signal processing by a suitable configuration of the setup and hold circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor module. The module contains a signal path for carrying external signals. The signal path includes a first latch circuit, at least one logic circuit connected downstream of the first latch, and a second latch circuit connected downstream of the logic circuit and functioning as a full latch. The first latch circuit and the second latch circuit set a setup time and a hold time of a fed-in external signal fed onto the signal path. The first latch circuit functions as a hold latch for transmitting a leading signal edge and for delaying a trailing signal edge of the fed-in external signal on a basis of a clock signal derived from a leading signal edge of an external signal clock signal of the fed-in external signal, in order to set an internal hold time for the fed-in external signal on the signal path before the fed-in external signal passes through the logic circuit.
Accordingly, in the case of the semiconductor module of the type mentioned in the introduction, the invention provides that the latch circuit contains at a beginning of the signal path upstream of the logic circuit a hold latch, which responds to the leading edge of a fast clock signal derived from the clock signal of the external signal, for the early latching of the external signal and for the decoupling of the hold time from the setup time. The full latch is disposed downstream of the logic circuit for the final latching of the external signal or of a signal derived from the latter.
In contrast to the two procedures according to the prior art as explained above, the setup and hold circuit of the semiconductor module according to the invention is accordingly provided with two latch circuits which are disposed at different points of the signal path and of which one is configured as a hold latch and the other as a full latch. The hold latch is disposed at the beginning of the signal path, while the full latch is disposed downstream of the latter, following a logic circuit or a plurality of logic circuits.
According to the invention, the task of the hold latch is to latch the incoming or external signal very early and to decouple the hold time from the setup time of the signal by the signal acquiring a dedicated internal hold time. The final latching of the (external) signal is effected after the latter has passed through the logic circuits, in the full latch.
The invention thereby makes it possible to utilize the advantages of the previous two procedures for centering the setup and hold times, without accepting their disadvantages. In other words, the configuration of the semiconductor module according to the invention makes it possible both to set the setup and hold times without difficulty and to utilize the external setup time in favor of fast internal signal processing.
In an advantageous manner, for changing over the hold latch between the states transparent and non-transparent, it is provided that the fast clock signal is applied to the clock terminal of the hold latch for the purpose of delaying the trailing edge of the external signal while providing an internal hold timexe2x80x94independent of the setup timexe2x80x94for this signal. In this case, the length of the fast clock signal, for providing an internal hold time, is preferably chosen in such a way as to ensure reliable latching of the full latch connected downstream. The fast clock signal thereby present at the hold latch enables the hold latch to be transparent when an external signal arrives. The leading edge, i.e. the setup edge, of the incoming signal can thereby pass through the hold latch, is latched and follows the further signal path unimpeded. In other words, the signal edge is not retained in the hold latch, but rather continues on its way on the signal path without any delay. Before the trailing signal edge or hold edge, can then pass through the hold latch, the fast clock signal switches the hold latch to a non-transparent state, as a result of which the signal downstream of the hold latch on the signal path maintains its level unimpeded. In other words, the trailing signal edge is temporally delayed by this measure. The duration or width of the blocking clock pulse determines a minimum width of the signal pulse downstream of the hold latch on the signal path. The consequence of this is that an internal hold time of the internal signal is generated which is independent of the setup time.
In order to ensure that, in the case of a plurality of external signals carried separately on the signal path, the signals can be processed simultaneously in the hold latch, a delay circuit is preferably connected upstream of the hold latch. A further delay circuit is preferably connected upstream of the clock input of the full latch. Both delay circuits are provided for adapting the phase angles of the external signals.
A configuration of the hold latch that is advantageous because it is simple provides, in a sequence from its input to its output, a p/n-channel element (for example in the form of a transmission gate, a transfer gate or a pass gate) and two reverse-connected parallel inverters. With the same aim, the full latch provides a series circuit of two identical circuits which each have the internal construction of the hold latch.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor module, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.